An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS

This paper presents an 8-GS/s, 12-bit input ∆Σ DAC with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR and -57-dBc IMD3, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.